Flash memory is a non-volatile memory (NVM) that is a specific type of electrically erasable programmable read-only memory (EEPROM). One commonly employed type of flash memory technology is NAND flash memory. NAND flash memory requires small chip area per cell and is typically divided into one or more banks or planes. Each bank is divided into blocks; each block is divided into pages. Each page includes a number of bytes for storing user data, error correction code (ECC) information, or both.
There are three basic operations for NAND devices: read, write and erase. The read and write operations are performed on a page-by-page basis. Page sizes are generally 2N bytes of user data (plus additional bytes for ECC information), where N is an integer, with typical user data page sizes of, for example, 2,048 bytes (2 KB), 4,096 bytes (4 KB), 8,192 bytes (8 KB) or more per page. A “read unit” is the smallest amount of data and corresponding ECC information that can be read from the NVM and corrected by the ECC, and might typically be between 4K bits and 32K bits (e.g., there is generally an integer number of read units per page). Pages are typically arranged in blocks, and an erase operation is performed on a block-by-block basis. Typical block sizes are, for example, 64, 128 or more pages per block. Pages must be written sequentially, usually from a low address to a high address within a block. Lower addresses cannot be rewritten until the block is erased. Associated with each page is a spare area (typically 100-640 bytes) generally used for storage of ECC information and/or other metadata used for memory management. The ECC information is generally employed to detect and correct errors in the user data stored in the page.
A hard disk is accessed by a host device based on a logical block address (LBA). For a hard disk write operation, old data is over-written by new data at the same physical LBA. An NVM is accessed based on a logical page number (LPN). However, each page might generally be written only once since a NAND device requires that a block of data be erased before new data is written to the block. Thus, for a NAND device to write new data to a given LBA, the new data is written to an erased page that is a different physical page than the page previously used for that LBA. Therefore, NAND devices require device driver software, or a separate controller chip with firmware, to maintain a record of logical-to-physical mappings of each LBA to the current page number where its data is stored. The mapping data might also be used to perform “garbage collection” to erase data that is “stale” or out-of-date. Further, because NVM blocks can be erased only a limited number of times before device failure, mapping data might also be employed to track failed blocks over the operational life of the NVM (e.g., over a rated number of program/erase (P/E) cycles for NAND flash).
For SSDs that store mapping data in the NVM, retrieving map data from the NVM can occur frequently under typical host workloads and, thus, negatively impact the bandwidth available to transfer actual user data to/from the NVM as the channel(s) are used to transfer the mapping data. Thus, an improved mechanism for retrieving map data from the NVM is needed.